jalilweb.com

ABSTRACT

This paper represents a report of an individual research project on the important aspects of High-Level (Behavioural) Synthesis of digital systems. The motivations behind automating the process of VLSI design are outlined and the challenges defined. A review of some of the significant works on the subtasks of behavioural synthesis is presented. A number of scheduling techniques are explained, and the interdependence between the HLS subtasks is stressed. The report also shows the importance of low power, reliability and testability considerations at high levels of abstraction in the design flow. The necessity of comparing and evaluating different high-level synthesis techniques is discussed.

1. INTRODUCTION

In the early days of digital systems design the silicon area was limited to a small number of transistors, and designers managed to manually map their systems directly into transistor level layout. The majority of those systems were relatively simple and the designer had the capability of exploring most of the different possible implementations in a limited time. However, technological advances dramatically reduced the size of transistors and thus increased their density in a single chip. This allowed integrated circuits to accommodate increasingly complex systems and paved the way to SoC implementations, therefore making the designer’s job increasingly difficult and time consuming.

The product design cycle and time-to-market is similarly if not more important than area or performance. The complexity of the development cycle and the pressure to meet market needs in the shortest possible times have lead to addressing the idea of automating the design process. As a result, the term ‘Silicon Compiler’ has gained increasing popularity as a research topic. We define a Silicon Compiler as an integrated system that translates the algorithmic or behavioural description of a system into the physical (silicon) layout representation. One of the significant early developments in silicon compilers is the ‘Bristle Blocks’ system by Dave Johannsen [12]. Although in his system parts of the chip had to be manually produced, the Bristle Blocks system managed to automatically generate data-path and control blocks from a high-level input description of the chip in a short time. New silicon compilers then emerged which produced complete circuit layouts automatically

Part of the silicon compilation process is the High-Level Synthesis, also known as the Behavioural Synthesis which is the process of transforming a behavioural description of a digital system into a Register Transfer Level (RTL) representation. The input representation to such a process describes the behaviour of a digital system in terms of variables, operations and conditional statements and may be written in any high level programming language (like C or C++) or any hardware description language (like VHDL or Verilog). The RTL representation describes a digital system in terms of functional units, storage units, and interconnection structures and the flow of signals between the components. This description is then transformed into a logic representation and into physical layout using RTL synthesis tools and Place-&-Route tools.

The aim of this paper is to cover the significant developments in high level synthesis during the past three decades and sum up the different approaches and techniques that were proposed. The rest of the paper is organized as follows. Section 2 defines the basic building blocks of a high-level synthesis system and discusses the different approaches undertaken to arrive at an optimal solution. Section 3 discusses the design for low power techniques at the behavioural level, whereas Section 4 outlines the importance of circuits testability and how it can be achieved at the high-level of abstraction. Section 5 looks at the current status of benchmarks used to evaluate or compare synthesis techniques and Section 6 identifies the present trends of digital systems synthesis before concluding in Section 7.