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Written by Jalil
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Tuesday, 02 June 2009 |
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if you want to know the number of bits constituting an integer look no further. Here is a very simple solution. int get_number_of_bits(int the_number){ int bits = 1; int div = (the_number/2); while(div != 0){ bits++; div = div/2; } return bits; } So this is just a simple division by 2 loop, that counts the number of times we could divide the number by two without the result being less than 1 (which is the number of bits -1). This works for positive integers from 0 and up. Now if you wanted to know the number of bits required to represent a number of elements (i.e. you want to know how many bits would represent a number of states, elements or anything you like) then use the same algorithm above, except that you need to change the line: int div = the_number/2 into int div = (the_number-1)/2 this is because, number of states or elements is never 0. Feedback is very welcome. |
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Last Updated ( Tuesday, 02 June 2009 )
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Written by Jalil
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Saturday, 05 April 2008 |
There was a photography competition organized by ECS recently. Entries were divided into 4 different categories with two prizes, the first prize is £75 and the second is £25 for each category. I have participated in this competition, but unfortunately I did not win any prize! The reason for that was the outstanding quality of the photos entered. Click on read more to see the participating photos. And here is a gallery of the photos that I submitted ( Eventually, ECS have asked my permission to allow them to publish two of my photos on the MSc Prospectus !! )
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Last Updated ( Saturday, 05 April 2008 )
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Written by Jalil
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Thursday, 27 March 2008 |
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This is a handy ebnf description of the VHDL language grammar (syntax) rules. The rules are also hyperlinked for easy navigation. Source (VHDL Language Reference Manual ) |
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Last Updated ( Monday, 07 April 2008 )
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Written by Jalil
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Wednesday, 26 March 2008 |
ABSTRACTThis paper represents a report of an individual research project on the important aspects of High-Level (Behavioural) Synthesis of digital systems. The motivations behind automating the process of VLSI design are outlined and the challenges defined. A review of some of the significant works on the subtasks of behavioural synthesis is presented. A number of scheduling techniques are explained, and the interdependence between the HLS subtasks is stressed. The report also shows the importance of low power, reliability and testability considerations at high levels of abstraction in the design flow. The necessity of comparing and evaluating different high-level synthesis techniques is discussed. |
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Last Updated ( Monday, 31 March 2008 )
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