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Two months into my PhD now, and I already have an idea of what needs to be done to achieve the ultimate goal! (Not the real goal though)

As part of the system I am creating, I need to create a VHDL parser! This is no trivial task. Simply because everything I read in the internet and in a couple of papers agrees that the VHDL standard BNF specification is an ambigious grammar.

This means that using a parser generator tool like Bison(YACC) is not the safest option. Since Bison resolves reduce/reduce conflicts by choosing to use the rule that appears first in the grammar, it is very risky to rely on this. "According to the Bison manual"

The only way such a parser generator can be usefull is by changing the standard BNF specification in order to eliminate those conflicts. I found a VHDL BNF grammar for YACC that was modified and only produces 3 shift/reduce and 3 reduce/reduce conflicts. This is nice, but I really need to go through the changes one by one trying to spot any unwanted mistakes.

The other way, is to create a parser from scratch. Maybe reuse some parts of the bison generated source code to reduce the time it will take to create a fresh parser.

For the time being.. I have no conclusion to write in this post ! 

Hello! My name is Abdeldjalil Belouettar. I created this website to publish my thoughts, my interests, my activities and my news. I am currently a PhD student at the University of Southampton (School of Electronics and Computer Science) and possess a Master of Engineering degree in Computer Engineering from ECS...