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Today is the second day of my PhD. I already have a desk and ordered a new PC which will arrive in about 20 odd days... I have done most paperwork and met briefly with my supervisor.. we've agreed a meeting early next week.. so that's a very good oportunity for me to finish reading a thesis related to my research and get some technical books from the library. So far so good and off I go to do some reading...

Two months into my PhD now, and I already have an idea of what needs to be done to achieve the ultimate goal! (Not the real goal though)

As part of the system I am creating, I need to create a VHDL parser! This is no trivial task. Simply because everything I read in the internet and in a couple of papers agrees that the VHDL standard BNF specification is an ambigious grammar.

This means that using a parser generator tool like Bison(YACC) is not the safest option. Since Bison resolves reduce/reduce conflicts by choosing to use the rule that appears first in the grammar, it is very risky to rely on this. "According to the Bison manual"

The only way such a parser generator can be usefull is by changing the standard BNF specification in order to eliminate those conflicts. I found a VHDL BNF grammar for YACC that was modified and only produces 3 shift/reduce and 3 reduce/reduce conflicts. This is nice, but I really need to go through the changes one by one trying to spot any unwanted mistakes.

The other way, is to create a parser from scratch. Maybe reuse some parts of the bison generated source code to reduce the time it will take to create a fresh parser.

For the time being.. I have no conclusion to write in this post ! 

ABSTRACT

This paper represents a report of an individual research project on the important aspects of High-Level (Behavioural) Synthesis of digital systems. The motivations behind automating the process of VLSI design are outlined and the challenges defined. A review of some of the significant works on the subtasks of behavioural synthesis is presented. A number of scheduling techniques are explained, and the interdependence between the HLS subtasks is stressed. The report also shows the importance of low power, reliability and testability considerations at high levels of abstraction in the design flow. The necessity of comparing and evaluating different high-level synthesis techniques is discussed.